View TSL208R_1329457.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

t
TSL208R 512 y 1 LINEAR SENSOR ARRAY
t TAOS031C - OCTOBER 2002
D D D D D D D D D
512 x 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply Replacement for TSL208
(TOP VIEW)
Description
The TSL208R linear sensor array consists of a 512 x 1 array of photodiodes and associated charge amplifier circuitry. The pixels measure 120 m (H) by 70 m (W) with 125-m center-to-center spacing and 55-m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock.
1 2 3 4 5 6 7
VDD SI CLK AO GND SO VDD
The TSL208R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding.
Functional Block Diagram
1 Pixel 1 Integrator Reset Pixel 2 Pixel 3 Pixel 512 Analog Bus VDD Output Amplifier 4 AO Sample/ Output RL 330 W 5 GND
_ +
Switch Control Logic
Gain Trim
6 SO
Q1
Q2
Q3
Q512
CLK SI
3 2
512-Bit Shift Register
The LUMENOLOGYr Company
t
Copyright E 2002, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) 673-0759 t
www.taosinc.com 1
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
Terminal Functions
TERMINAL NAME AO CLK GND SI SO VDD NO. 4 3 5 2 6 1, 7 I/O O I I I O I Analog output. Clock. The clock controls the charge transfer, pixel output and reset. Ground (substrate). All voltages are referenced to the substrate. Serial input. SI defines the start of the data out sequence. Serial output. SO signals the end of the data out sequence. Supply voltage for both analog and digital circuits. DESCRIPTION
Detailed Description
The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2). As the SI pulse is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 513th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 513th clock pulse is required to terminate the output of the 512th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 514th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee) (tint) where: Vout Vdrk Re Ee tint is is is is is the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(J/cm2) the incident irradiance in W/cm2 integration time in seconds
AO is driven by a source follower with an internal 330- pulldown resistor (no external resistor is required). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device.
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
Copyright E 2002, TAOS Inc.
t
The LUMENOLOGYr Company
t
2
www.taosinc.com
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
Absolute Maximum Ratings
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -100 mA to 100 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Lead temperature on connection pad for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock frequency, fclock Sensor integration time, tint Operating free-air temperature, TA Load resistance, RL Load capacitance, CL 4.5 0 2 0 400 5 0.1026 0 300 NOM 5 MAX 5.5 VDD VDD 0.8 1000 5000 100 70 4700 330 UNIT V V V V nm kHz ms C pF
The LUMENOLOGYr Company
t
Copyright E 2002, TAOS Inc.
t
www.taosinc.com
3
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25C, p = 640 nm, tint = 5 ms, RL = 330 , Ee = 18 W/cm2 (unless otherwise noted)
PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 512 pixels) Analog output voltage (dark, average over 512 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re SE Vsat DSNU IL IDD IIH IIL VOH Responsivity Saturation exposure Analog output saturation voltage Dark signal nonuniformity Image lag Supply current, output idle High-level input current Low-level input current High-level High level output voltage SO voltage, VI = VDD VI = 0 IO = 50 A IO = 4 mA IO = 50 A IO = 4 mA 4.5 4.95 4.6 0.01 0.4 40 40 0.1 V pF pF V All pixels See Note 7 See Note 6 See Note 5 2.5 See Notes 2 & 3 See Note 3 See Note 4 16 TEST CONDITIONS See Note 1 MIN 1.6 0 TYP 2 50 7% 0.4% 1 22 155 3.4 25 0.5% 28 45 10 10 mA A A 120 28 MAX 2.4 150 20% FS mVrms V/ (J/cm 2) nJ/cm 2 V mV UNIT V mV
VOL Ci(SI) Ci(CLK)
Low-level Low level output voltage SO voltage, Input capacitance, SI Input capacitance, CLK
NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 5. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re. 6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination. 7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100
Timing Requirements (see Figure 1 and Figure 2)
MIN tsu(SI) th(SI) tw tr, tf Setup time, serial input (see Note 8) Hold time, serial input (see Note 8 and Note 9) Pulse duration, clock high or low Input transition (rise and fall) time 20 0 50 0 500 NOM MAX UNIT ns ns ns ns
NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 9. SI must go low before the rising edge of the next clock pulse.
Copyright E 2002, TAOS Inc.
t
The LUMENOLOGYr Company
t
4
www.taosinc.com
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 2)
PARAMETER ts tpd(SO) Analog output settling time to 1% Propagation delay time, SO TEST CONDITIONS CL = 10 pF MIN TYP 185 50 MAX UNIT ns ns
TYPICAL CHARACTERISTICS
CLK
SI
AO
Hi-Z
tw CLK tsu(SI)
SI
AO
The LUMENOLOGYr Company
IIIIIII IIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIII
Hi-Z
513 Clock Cycles
Figure 1. Timing Waveforms (each section)
1
2
512
513 5V 2.5 V 0V
5V 50% 0V th(SI)
ts
ts
Pixel 1
Pixel 512
Figure 2. Operational Waveforms (each section)
t
Copyright E 2002, TAOS Inc.
t
www.taosinc.com
5
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
TYPICAL CHARACTERISTICS
PHOTODIODE SPECTRAL RESPONSIVITY
1 TA = 25C 0.8 Normalized Responsivity
0.6
0.4
0.2
0 300
400
500
600
700
800
900
1000 1100
- Wavelength - nm
Figure 3
Copyright E 2002, TAOS Inc.
t
The LUMENOLOGYr Company
t
6
www.taosinc.com
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
MECHANICAL INFORMATION
0.091 (2,31) 0.087 (2,21) DIA Mounting Holes 2 Places 1.1325 (28,77) 1.1125 (28,26) 0.169(4,29) 0.161(4,09) 1 0.230 (5,84) 0.210 (5,33) Pixel 1 Plated Hole 7 Places 0.027(0,69) 0.021(0,53) DIA TOP VIEW 7 Pixel 512 1.210 (30,73) 1.190 (30,23) 0.100 (2,54) BSC 0.242 (6,15) 0.222(5,64)
DETAIL A 0.080 (2,03) 0.060 (1,52)
2.855 (72,52) 2.835 (72,01) 3.005 (76,33) 2.995 (76,07)
0.505 (12,83) 0.495(12,57)
0.137(3,48) 0.126 (3,22)
Cover Glass (Index of Refraction = 1.52)
0.015 (0,38) Typical Free Area
Linear Array 0.045 (1,09)0.005 Cover Glass
Bonded Chip Bypass Cap DETAIL A NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Pixel centers are located along the center line of the mounting holes.
The LUMENOLOGYr Company
IIIIIIIIIIIIIIIIIIIII IIIIII
Figure 4. TSL208R Mechanical Specifications
t t
0.027 (0,069)
Copyright E 2002, TAOS Inc.
www.taosinc.com
7
TSL208R 512 y 1 LINEAR SENSOR ARRAY
TAOS031C - OCTOBER 2002
PRODUCTION DATA -- information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER'S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
Copyright E 2002, TAOS Inc.
t
The LUMENOLOGYr Company
t
8
www.taosinc.com

▲Up To Search▲

Price & Availability of TSL208R

	To Download TSL208R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .